/*
 * Copyright (C) 1996  Warren Jasper
 * All rights reserved.
 *
 */

/*
 * dio48H.h
 */

/* #define DIO48H_BASE     0x350  */   /* Default base address */

/* Default device major number */
#ifndef DEFAULT_MAJOR_DEV
#define DEFAULT_MAJOR_DEV  35    /* Default Major Device Number */
#endif
#define DIO_PORTS           6    /* 48 Digital I/O Ports (3 bytes) */
#define PORT_MIN         0x200   /* minimum base address used in autodetecting */
#define PORT_MAX         0x3e0   /* maximum base address allowed by board      */
#define PORT_STEP        0x10    /* base step ( 16 bytes)                      */
#define PORT_SIZE        0x8     /* uses 8 bytes of registers                  */

/* I/O Register locations */

/* NOTE: base_reg to be found dynamically at boot time. Not hard coded into driver */


#define DIO_PORT1A             (base_reg)    /* Port A 8 bit I/O of 8255 */
#define DIO_PORT1B             (base_reg+1)  /* Port B 8 bit I/O of 8255 */
#define DIO_PORT1C             (base_reg+2)  /* Port C 4+4 bit of 8255 */
#define DIO_CNTRL_REG_1        (base_reg+3)  /* Mode and Direction Control Register */
#define DIO_PORT2A             (base_reg+4)  /* Port A 8 bit I/O of 8255 */
#define DIO_PORT2B             (base_reg+5)  /* Port B 8 bit I/O of 8255 */
#define DIO_PORT2C             (base_reg+6)  /* Port C 4+4 bit of 8255 */
#define DIO_CNTRL_REG_2        (base_reg+7)  /* Mode and Direction Control Register */

/* General defines */

#define TRUE  1
#define FALSE 0
#define BYTE unsigned char
#define WORD unsigned short
#define LONG unsigned long

/* 
#define DEBUG 
 */


/* Values kept for each channel. */

typedef struct CHANNEL_REC {
  int  open;            /* Is channel device open()         */
  WORD value;           /* value of DIO Channel             */
  WORD addr;            /* address of the channel           */
  int mode;             /* mode for 8255                    */
} ChanRec;

